1. Field of the Invention
The present invention relates to a method and system for characterizing porous materials and, more particularly, to a method and system for characterizing the porosity of porous materials and the effectiveness of treating porous materials.
2. Description of Related Art
As is known to those in the semiconductor art, interconnect delay is a major limiting factor in the drive to improve the speed and performance of integrated circuits (IC). One way to minimize interconnect delay is to reduce interconnect capacitance by using low dielectric constant (low-k) materials during production of the IC. Thus, in recent years, low-k materials have been developed to replace relatively high dielectric constant insulating materials, such as silicon dioxide. In particular, low-k films are being utilized for inter-level and intra-level dielectric layers between metal layers of semiconductor devices. Additionally, in order to further reduce the dielectric constant of insulating materials, material films are formed with pores, i.e., porous low-k dielectric films. Such low-k films can be deposited by a spin-on dielectric (SOD) method similar to the application of photo-resist, or by chemical vapor deposition (CVD). Thus, the use of low-k materials is readily adaptable to existing semiconductor manufacturing processes.
While low-k materials are promising for fabrication of semiconductor circuits, the present inventors have recognized that these films also provide many challenges. First, low-k films tend to be less robust than more traditional dielectric layers and can be damaged during wafer processing, such as by plasma etching and plasma ashing processes generally used in patterning the dielectric layer. Further, some low-k films tend to be highly reactive when damaged, particularly after patterning, thereby allowing the low-k material to absorb water and/or react with other vapors and/or process contaminants that can alter the electrical properties of the dielectric layer. For example, following pattern etching, the exposed surfaces can change from being hydrophobic to becoming hydrophilic, the exposed surface layer can become depleted of carbon (C), and the pores can retain contaminants from the etch process.
Moreover, the present inventors have recognized that the porosity of some low-k dielectric films often exacerbates the problems of integrating metallization with the dielectric. In general, the integration of copper metallization with low-k dielectric films requires the use of a damascene structure, wherein metal wiring patterns are formed within the dielectric film prior to copper deposition. In order to minimize the diffusion of copper into the dielectric film, a barrier layer is typically formed on the internal surfaces of these patterns following pattern etching.
However, exposure of the pores and/or damage of the low-k film following the etching of patterns in the dielectric film causes problems with diffusion of the precursors of the barrier material and copper through imperfections in the barrier film local to these exposed pores, as well as poor adhesion of the barrier layer to the dielectric film.